Devicetree Specification v0.4-dirty
¶
1. Introduction
1.1. Purpose and Scope
1.2. Relationship to IEEE™ 1275 and ePAPR
1.3. 32-bit and 64-bit Support
1.4. Definition of Terms
2. The Devicetree
2.1. Overview
2.2. Devicetree Structure and Conventions
2.2.1. Node Names
2.2.2. Generic Names Recommendation
2.2.3. Path Names
2.2.4. Properties
2.3. Standard Properties
2.3.1. compatible
2.3.2. model
2.3.3. phandle
2.3.4. status
2.3.5. #address-cells and #size-cells
2.3.6. reg
2.3.7. virtual-reg
2.3.8. ranges
2.3.9. dma-ranges
2.3.10. dma-coherent
2.3.11. dma-noncoherent
2.3.12. name (deprecated)
2.3.13. device_type (deprecated)
2.4. Interrupts and Interrupt Mapping
2.4.1. Properties for Interrupt Generating Devices
2.4.2. Properties for Interrupt Controllers
2.4.3. Interrupt Nexus Properties
2.4.4. Interrupt Mapping Example
2.5. Nexus Nodes and Specifier Mapping
2.5.1. Nexus Node Properties
2.5.2. Specifier Mapping Example
3. Device Node Requirements
3.1. Base Device Node Types
3.2. Root node
3.3.
/aliases
node
3.4.
/memory
node
3.4.1.
/memory
node and UEFI
3.4.2.
/memory
Examples
3.5.
/reserved-memory
Node
3.5.1. /reserved-memory parent node
3.5.2. /reserved-memory/ child nodes
3.5.3. Device node references to reserved memory
3.5.4.
/reserved-memory
and UEFI
3.5.5.
/reserved-memory
Example
3.6.
/chosen
Node
3.7.
/cpus
Node Properties
3.8.
/cpus/cpu*
Node Properties
3.8.1. General Properties of
/cpus/cpu*
nodes
3.8.2. TLB Properties
3.8.3. Internal (L1) Cache Properties
3.8.4. Example
3.9. Multi-level and Shared Cache Nodes (
/cpus/cpu*/l?-cache
)
3.9.1. Example
4. Device Bindings
4.1. Binding Guidelines
4.1.1. General Principles
4.1.2. Miscellaneous Properties
4.2. Serial devices
4.2.1. Serial Class Binding
4.2.2. National Semiconductor 16450/16550 Compatible UART Requirements
4.3. Network devices
4.3.1. Network Class Binding
4.3.2. Ethernet specific considerations
4.4. Power ISA Open PIC Interrupt Controllers
4.5.
simple-bus
Compatible Value
5. Flattened Devicetree (DTB) Format
5.1. Versioning
5.2. Header
5.3. Memory Reservation Block
5.3.1. Purpose
5.3.2. Format
5.3.3. Memory Reservation Block and UEFI
5.4. Structure Block
5.4.1. Lexical structure
5.4.2. Tree structure
5.5. Strings Block
5.6. Alignment
6. Devicetree Source (DTS) Format (version 1)
6.1. Compiler directives
6.2. Labels
6.3. Node and property definitions
6.4. File layout
Devicetree Specification
Navigation
1. Introduction
2. The Devicetree
3. Device Node Requirements
4. Device Bindings
5. Flattened Devicetree (DTB) Format
6. Devicetree Source (DTS) Format (version 1)
Related Topics
Documentation overview
Next:
<no title>
Quick search